r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 809

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r8a77850anbg

Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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16.5.3
The time period taken by manual reset on watchdog timer overflow (WDT manual reset holding
time) is equal to or more than 30 cycles of the peripheral clock (Pck).
The transition time from watchdog timer overflow to the manual reset state (WDT reset setup
time) is equal to or more than eight cycles of the peripheral clock (Pck).
(1)
The timing of indicating the reset state or normal operation on the STATUS[1:0] pins is
synchronous with the peripheral clock (Pck), and is therefore asynchronous with the clocks input
from the EXTAL pin and the CLKOUT pin.
WDT overflow
signal
EXTAL
input
CLKOUT
output
CLKOUTENB
output
MRESETOUT
output
STATUS[1:0]
output
Manual Reset Caused by Watchdog Timer Overflow during Normal Operation
Figure 16.8 STATUS Output by Manual Reset Caused by WDT Overflow
Manual Reset by Watchdog Timer Overflow
WDT reset setup time
LL (normal)
during Normal Operation
HH (reset)
WDT manual reset holding time
Rev.1.00 Jan. 10, 2008 Page 779 of 1658
16. Watchdog Timer and Reset (WDT)
REJ09B0261-0100
LL (normal)

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