r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 734

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r8a77850anbg

Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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14. Direct Memory Access Controller (DMAC)
Table 14.8 List of On-Chip Peripheral Module Request Modes
Rev.1.00 Jan. 10, 2008 Page 704 of 1658
REJ09B0261-0100
CHCR
RS[3:0] MID
1000
DMARS
000000 11
000001 11
001000 01
001001 01
001010 01
001011 01
001100 01
RID
10
10
10
10
10
DMA Transfer
Request Source DMA Transfer Request Signal Source
SSI0 transmitter
SSI0 receiver
SSI1 transmitter
SSI1 receiver
SCIF0 transmitter TXI (transmit FIFO data empty) Any
SCIF0 receiver
SCIF1 transmitter TXI (transmit FIFO data empty) Any
SCIF1 receiver
SCIF2 transmitter TXI (transmit FIFO data empty) Any
SCIF2 receiver
SCIF3 transmitter TXI (transmit FIFO data empty) Any
SCIF3 receiver
SCIF4 transmitter TXI (transmit FIFO data empty) Any
SCIF4 receiver
Transmit data empty request
(In transmit mode, the DMRQ
bit in the SSISR0 register is 1.)
Unread data is present (In
receive mode, the DMRQ bit in
the SSISR0 register is 1.)
Transmit data empty request
(In transmit mode, the DMRQ
bit in the SSISR1 register is 1.)
Unread data is present (In
receive mode, the DMRQ bit in
the SSISR1 register is 1.)
RXI (receive FIFO data full)
RXI (receive FIFO data full)
RXI (receive FIFO data full)
RXI (receive FIFO data full)
RXI (receive FIFO data full)
Any
SSIRDR0
Any
SSIRDR1
SCFRDR0
SCFRDR1
SCFRDR2
SCFRDR3
SCFRDR4
Destination
SSITDR0
Any
SSITDR1
Any
SCFTDR0
Any
SCFTDR1
Any
SCFTDR2
Any
SCFTDR3
Any
SCFTDR4
Any
Bus
Mode
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal

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