r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 873

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Bit
9
8
Bit Name
DRES
DEN
Initial
Value
1
0
R/W
R/W
R/W
Internal
Update
None
Yes
Description
Display Reset
Display Enable
00: Starts display synchronization operation.
01: Starts display synchronization operation.
10: Halts display and synchronization operation.
However, when the ODPM bit in DSMR is 1, the
ODDF pin output is clamped.
11: Setting prohibited
3. The HSYNC, VSYNC, ODDF pins are input
pins.
In the case of a register not yet set,
unexpected operation may occur; hence
DRES should be set to 0 after setting all the
registers in the display unit (DU).
When DEN = 0, the display data is the value
set in the display-off output register (DOOR).
In the case of a register not yet set,
unexpected operation may occur; hence
DRES and DEN should be set to 0 and 1
respectively after setting all the registers in
the display unit (DU).
When DEN = 1, the display data is the value
stored in memory from the next frame.
Halts display operation and synchronization
operation. Except for the following bits in
DSSR, register settings are held.
For these settings, operation is as follows.
1. All display data output is 0.
2. The following bits in DSSR are cleared to
0.
⎯ TV sync signal error flag (TVR)
⎯ Frame flag (FRM)
⎯ Vertical blanking flag (VBK)
⎯ Raster interrupt flag (RINT)
⎯ Horizontal blanking flag (HBK)
Rev.1.00 Jan. 10, 2008 Page 843 of 1658
19. Display Unit (DU)
REJ09B0261-0100