r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 292

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

9. On-Chip Memory
(2)
In order to allocate instructions in the IL memory, write an instruction to the IL memory, execute
the following sequence, then branch to the rewritten instruction.
• SYNCO
• ICBI @Rn
In this case, the target for the ICBI instruction can be any address (IL memory address may be
possible) within the range where no address error exception occurs, and cache hit/miss is possible.
(3)
In order to allocate instructions in the U memory, write an instruction to the U memory, execute
the following sequence, then branch to the rewritten instruction.
• SYNCO
• ICBI @Rn
In this case, the target for the ICBI instruction can be any address (U memory address may be
possible) within the range where no address error exception occurs, and cache hit/miss is possible.
9.5.4
(1)
The SuperHyway bus master module, such as DMAC, cannot access OL memory and IL memory
in sleep mode.
(2)
The SuperHyway bus master module, such as DMAC, can access U memory in sleep mode.
9.6
In 32-bit address extended mode, L0SADR fields in LSA0, L1SADR fields in LSA1, L0DADR
fields in LDA0, and L1DADR fields in LDA1 are extended from 19-bit [28:10] to 22-bit [31:10].
Rev.1.00 Jan. 10, 2008 Page 262 of 1658
REJ09B0261-0100
IL Memory
U Memory
OL Memory, IL Memory
U Memory
Sleep Mode
Note on Using 32-Bit Address Extended Mode