r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 130

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

5. Exception Handling
5.5.2
A priority ranking is provided for all exceptions for use in determining which of two or more
simultaneously generated exceptions should be accepted. Five of the general exceptions—general
illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot
FPU disable exception, and unconditional trap exception—are detected in the process of
instruction decoding, and do not occur simultaneously in the instruction pipeline. These
exceptions therefore all have the same priority. General exceptions are detected in the order of
instruction execution. However, exception handling is performed in the order of instruction flow
(program order). Thus, an exception for an earlier instruction is accepted before that for a later
instruction. An example of the order of acceptance for general exceptions is shown in figure 5.2.
Rev.1.00 Jan. 10, 2008 Page 100 of 1658
REJ09B0261-0100
Pipeline flow:
Order of detection:
Order of exception handling:
Instruction n
Instruction n + 1
Instruction n + 2
Instruction n + 3
General illegal instruction exception (instruction n + 1) and
TLB miss (instruction n + 2) are detected simultaneously
TLB miss (instruction n)
TLB miss (instruction n)
Re-execution of instruction n
General illegal instruction exception
(instruction n + 1)
Re-execution of instruction n + 1
TLB miss (instruction n + 2)
Re-execution of instruction n + 2
Execution of instruction n + 3
Exception Source Acceptance
Figure 5.2 Example of General Exception Acceptance Order
I1
I1
I1
I2
I2
I1
I3
I3
I2
TLB miss (instruction access)
ID
ID
I2
I3
General illegal instruction exception
E1
E1
ID
I3
Program order
E1
E2
E2
ID
TLB miss (data access)
1
2
3
4
E2
E3
E3
E1 E2
WB
WB
E3
E3
WB
WB
Legend:
I1, I2, I3:
ID :
E1, E2, E3: Instruction execution
WB
Instruction fetch
(E2, E3 Memory access)
Write-back
Instruction decode