r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 12

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

7.9
7.10 Usage Notes ....................................................................................................................... 209
Section 8 Caches
8.1
8.2
8.3
8.4
8.5
8.6
Rev.1.00 Jan. 10, 2008 Page xii of xxx
REJ09B0261-0100
7.8.1
7.8.2
7.8.3
7.8.4
7.8.5
7.8.6
32-Bit Boot Function ......................................................................................................... 207
7.9.1
7.9.2
7.10.1
Features.............................................................................................................................. 211
Register Descriptions......................................................................................................... 215
8.2.1
8.2.2
8.2.3
8.2.4
Operand Cache Operation.................................................................................................. 222
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Instruction Cache Operation .............................................................................................. 227
8.4.1
8.4.2
8.4.3
8.4.4
Cache Operation Instruction .............................................................................................. 229
8.5.1
8.5.2
Memory-Mapped Cache Configuration ............................................................................. 232
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
Overview of 32-Bit Address Extended Mode..................................................... 199
Transition to 32-Bit Address Extended Mode .................................................... 200
Privileged Space Mapping Buffer (PMB) Configuration ................................... 200
PMB Function..................................................................................................... 202
Memory-Mapped PMB Configuration ............................................................... 203
Notes on Using 32-Bit Address Extended Mode ................................................ 204
Initial Entries to PMB......................................................................................... 207
Notes on 32-Bit Boot .......................................................................................... 207
Note on Using LDTLB Instruction ..................................................................... 209
Cache Control Register (CCR) ........................................................................... 216
Queue Address Control Register 0 (QACR0)..................................................... 218
Queue Address Control Register 1 (QACR1)..................................................... 219
On-Chip Memory Control Register (RAMCR) .................................................. 220
Read Operation ................................................................................................... 222
Prefetch Operation .............................................................................................. 223
Write Operation .................................................................................................. 224
Write-Back Buffer .............................................................................................. 225
Write-Through Buffer......................................................................................... 225
OC Two-Way Mode ........................................................................................... 226
Read Operation ................................................................................................... 227
Prefetch Operation .............................................................................................. 227
IC Two-Way Mode............................................................................................. 228
Instruction Cache Way Prediction Operation ..................................................... 228
Coherency between Cache and External Memory.............................................. 229
Prefetch Operation .............................................................................................. 231
IC Address Array................................................................................................ 232
IC Data Array ..................................................................................................... 234
OC Address Array .............................................................................................. 234
OC Data Array.................................................................................................... 236
Memory-Mapped Cache Associative Write Operation....................................... 237
................................................................................................................... 211