r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 153

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

5.7
(1)
(2)
(3)
(4)
A. Check the BL bit in SR with software. If SPC and SSR have been saved to memory, set
B. Issue an RTE instruction. When RTE is executed, the SPC contents are saved in PC, the
A. General exception
B. Interrupt
A. Re-execution type general exception
B. Completion type general exception or interrupt
A. The instruction in the delay slot of the RTE instruction is executed only after the value
Return from Exception Handling
If a General Exception or Interrupt Occurs When BL Bit in SR = 1
SPC when an Exception Occurs
RTE Instruction Delay Slot
the BL bit in SR to 1 before restoring them.
SSR contents are saved in SR, and branch is made to the SPC address to return from the
exception handling routine.
When a general exception other than a user break occurs, the PC value for the instruction at
which the exception occurred in SPC, and a manual reset is executed. The value in
EXPEVT at this time is H'00000020; the SSR contents are undefined.
If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after
the BL bit in SR has been cleared to 0 by software. If a nonmaskable interrupt (NMI)
occurs, it can be held pending or accepted according to the setting made by software.
In sleep or standby mode, however, an interrupt is accepted even if the BL bit in SR is set
to 1.
The PC value for the instruction at which the exception occurred is set in SPC, and the
instruction is re-executed after returning from the exception handling routine. If an
exception occurs in a delay slot instruction, however, the PC value for the delayed branch
instruction is saved in SPC regardless of whether or not the preceding delay slot instruction
condition is satisfied.
The PC value for the instruction following that at which the exception occurred is set in
SPC. If an exception occurs in a branch instruction with delay slot, however, the PC value
for the branch destination is saved in SPC.
saved in SSR has been restored to SR. The acceptance of the exception related to the
instruction access is determined depending on SR before restoring, while the acceptance of
Usage Notes
Rev.1.00 Jan. 10, 2008 Page 123 of 1658
5. Exception Handling
REJ09B0261-0100