r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 310

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

10. Interrupt Controller (INTC)
(2)
ICR1 is a 32-bit readable/writable register that specifies the individual input signal detection
modes for the respective external interrupt input pins IRQ/IRL7 to IRQ/IRL0. These settings are
only valid when IRLM0 or IRLM1 of ICR0 is set to 1 so that IRQ/IRL3 to IRQ/IRL0 or
IRQ/IRL7 to IRQ/IRL4 pins are used as individual interrupts (IRQ7 to IRQ0 interrupts) inputs.
Notes: 1. When an IRQ pin is set for level input (IRQnS1 = 1) and the source holding mode
Rev.1.00 Jan. 10, 2008 Page 280 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31, 30
29, 28
27, 26
25, 24
23, 22
21, 20
19, 18
17, 16
15 to 0
R/W:
R/W:
Interrupt Control Register 1 (ICR1)
Bit:
Bit:
Name
IRQ0S
IRQ1S
IRQ2S
IRQ3S
IRQ4S
IRQ5S
IRQ6S
IRQ7S
⎯
(LVLMODE of ICR0) of the interrupt control register 0 (ICR0) is 0, the interrupt source is
held until the CPU accepts the interrupt (this is also true for other interrupts). Therefore,
even if an interrupt source is disabled before this LSI returns from sleep mode,
branching of processing to the interrupt handler when this LSI returns from sleep mode
is guaranteed. A held interrupt can be cleared by setting the corresponding interrupt
mask bit (the IM bit in the interrupt mask register) to 1 (refer to section 10.7.3, Clearing
R/W
31
15
⎯
R
0
0
IRQ0S
R/W
30
14
⎯
R
0
0
R/W
Initial
Value
00
00
00
00
00
00
00
00
All 0
29
13
⎯
R
0
0
IRQ1S
R/W
28
12
⎯
R
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
27
11
⎯
R
0
0
IRQ2S
R/W
26
10
⎯
R
0
0
Description
IRQn Sense Select
Selects whether the corresponding individual pin
interrupt signal on the IRQ/IRL7 to IRQ/IRL0 pins is
detected on rising or falling edges, or at the high or
low level.
00: The interrupt request is detected on falling edges
01: The interrupt request is detected on rising edges
10: The interrupt request is detected when the IRQn
11: The interrupt request is detected when the IRQn
Note: n = 0 to 7
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
25
⎯
R
0
9
0
IRQ3S
input is at the low level.
input is at the high level.
of the IRQn input.
of the IRQn input.
R/W
24
⎯
R
0
8
0
R/W
23
⎯
R
0
7
0
IRQ4S
R/W
22
⎯
R
0
6
0
R/W
21
⎯
R
0
5
0
IRQ5S
R/W
20
⎯
R
0
4
0
R/W
19
⎯
R
0
3
0
IRQ6S
R/W
18
⎯
R
0
2
0
R/W
17
⎯
R
0
1
0
IRQ7S
R/W
16
⎯
R
0
0
0