r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 537

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

12.4.13 DDRPAD DIC, ODT, OCD Setting Register (DBDICODTOCD)
The SDRAM refresh status register (DBRFSTS) is a readable/writable register. It is initialized
only upon power-on reset.
Initial value:
Initial value:
Bit
31 to 25 ⎯
24
23 to 20 ⎯
19
R/W:
R/W:
BIt:
BIt:
Bit Name
DDRSIG
DIC_AD
31
15
⎯
⎯
R
R
0
0
30
14
⎯
⎯
R
R
0
0
29
13
⎯
⎯
Initial
Value
All 0
0
All 0
0
R
R
0
0
ODTEN1
R/W
28
12
⎯
R
0
0
ODTEN0
R/W
27
⎯
11
R
0
0
R/W
R
R/W
R
R/W
EARLY
R/W
ODT_
26
10
⎯
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
Write Preamble Time Setting Bit
Sets the preamble time of the DQS signal to be output
when data is written to the DDR2-SDRAM. The number
of cycles is the number of DDR clock cycles.
0: Write preamble time = 0.5 cycle
1: Write preamble time = 1 cycle
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
Address and Command Pin Impedance Value
This bit should be set to the same value as the value set
for DIC of EMRS(1) in the DDR2-SDRAM.
0: Normal
1: Weak
T_ODT1
R/W
25
⎯
R
0
9
0
DDRSIG
T_ODT0
R/W
R/W
24
0
8
0
23
⎯
⎯
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 507 of 1658
22
⎯
⎯
R
R
0
6
0
12. DDR2-SDRAM Interface (DBSC2)
21
⎯
⎯
R
R
0
5
0
20
⎯
⎯
R
R
0
4
0
DIC_AD
R/W
19
⎯
R
0
3
0
REJ09B0261-0100
DIC_DQ
R/W
R/W
18
⎯
0
2
1
DIC_CK
R/W
R/W
17
⎯
0
1
1
R/W
R/W
DIC
16
⎯
0
0
1