r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 399

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Bit
19, 18
17
16
15
14
13 to 7
Bit Name
⎯
BREQEN
DMABST
⎯
HIZCNT
⎯
Initial
Value
All 0
0
0
0
0
All 0
R/W
R
R/W
R/W
R
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
BREQ Enable
Specifies whether an external request can be accepted
or not. In the initialized state at a power-on reset, an
external request is not accepted. When this LSI is
booted up in slave mode, an external request is
accepted regardless of the BREQEN value.
0: An external request is not accepted
1: An external request is accepted
DMAC Burst Mode Transfer Priority Setting
Specifies the priority of burst mode transfers by DMA
channels 0 to 5. When this bit is cleared to 0, the
priority is as follows: bus release, DMAC (burst mode),
CPU, DMAC, PCIC. When this bit is set to 1, the bus is
not released until completion of the DMAC burst
transfer. This bit is initialized at a power-on reset.
0: DMAC burst mode transfer priority setting is off
1: DMAC burst mode transfer priority setting is on
Reserved
This bit is always read as 0. The write value should
always be 0.
High Impedance (Hi-Z) Control
Specifies the state of signals WEn and RD/FRAME in
the bus-released state.
0: Signals WEn and RD/FRAME are high-impedance in
1: Signals WEn and RD/FRAME are driven in the bus-
Reserved
These bits are always read as 0. The write value should
always be 0.
the bus-released state
released state
Rev.1.00 Jan. 10, 2008 Page 369 of 1658
11. Local Bus State Controller (LBSC)
REJ09B0261-0100