r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1301

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

25.3.2
HACCSAR is a 32-bit read/write register that specifies the address of the codec register to be read
/written. When requesting a write to/read from a codec register, write the command register
address to HACCSAR and set the ST bit in the HACCR register to 1. The HAC then transmits this
register address to the codec via slot 1.
After the codec has responded to a read request (HACRSR.STARY = 1), the status address
received via slot 1 can be read out from HACCSAR.
Initial value:
Initial value:
Bit
31 to 20
19
R/W:
R/W:
Bit:
Bit:
Command/Status Address Register (HACCSAR)
Bit Name
⎯
RW
CA3/
SA3
R/W
31
15
⎯
R
0
0
CA2/
SA2
R/W
⎯
30
14
R
0
0
CA1/
SA1
R/W
29
⎯
13
R
0
0
Initial
Value
All 0
0
CA0/
SA0
R/W
28
12
⎯
R
0
0
EQ3
SLR
R/W
R
R/W
27
11
⎯
R
R
0
0
SLR
EQ4
26
⎯
10
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
0: Notifies the off-chip codec device of a write access to
1: Notifies the off-chip codec device of a read access to
Codec Read/Write Command
SLR
EQ5
⎯
25
the register specified in the address field (CA6/SA6
to CA0/SA0).
Write the data to HACCSDR in advance.
When HACACR.TX12_ATOMIC is 1, the HAC
transmits HACCSAR and HACCSDR as a pair in the
same TX frame.
When HACACR.TX12_ATOMIC is 0, transmission of
HACCSAR and HACCSDR in the same TX frame is
not guaranteed.
the register specified in the address field (CA6/SA6
to CA0/SA0).
R
R
0
9
0
EQ6
SLR
24
⎯
R
R
0
8
0
SLR
EQ7
23
⎯
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 1271 of 1658
SLR
EQ8
22
⎯
R
0
R
0
6
EQ9
SLR
21
⎯
R
R
0
0
5
25. Audio Codec Interface (HAC)
EQ10
SLR
20
⎯
R
R
0
4
0
EQ11
R/W
RW
SLR
19
R
0
3
0
REJ09B0261-0100
EQ12
CA6/
R/W
SA6
SLR
18
R
0
2
0
CA5/
SA5
R/W
17
⎯
R
0
1
0
CA4/
SA4
R/W
16
⎯
R
0
0
0