r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 293

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

The interrupt controller (INTC) determines the priority of interrupt sources and controls the flow
of interrupt requests to the CPU (SH-4A). The INTC has registers for setting the priority of each
of the interrupts and processing of interrupt requests follows the priority order set in these registers
by the user.
10.1
The INTC has the following features:
• Fifteen levels of external interrupt priority can be set
• NMI noise canceller function
• NMI request masking when the block bit (BL) in the status register (SR) is set to 1
• Automatically updates the IMASK bit in SR according to the accepted interrupt level
• Thirty priority levels for interrupts from on-chip peripheral modules
• User-mode interrupt disabling function
• Holding mode of the level-sense IRQ and IRL interrupt sources (ICR0.LVLMODE)
By setting the interrupt priority registers, the priorities of external interrupts can be selected
from 15 levels for individual pins.
An NMI input-level bit indicates the NMI pin state. The bit can be read within the interrupt
exception handling routine to confirm the pin state and thus achieve a form of noise
cancellation.
Masking or non-masking of NMI requests when the BL bit in SR is set to 1 can be selected.
By setting the ten interrupt priority registers for the on-chip peripheral module interrupts, any
of 30 priority levels can be assigned to the individual requesting sources.
An interrupt mask level in the user interrupt mask level register (USERIMASK) can be
specified to disable interrupts which do not have higher priority than the specified mask level.
This setting can be made in user mode.
For the IRQ and IRL interrupts when the level sensing is set, the following two modes are
available:
(a) A mode in which the source of interrupt is temporarily held inside of the INTC even if the
(b) A mode in which the source of interrupt is not held inside of the INTC.
(c) The initial value of ICR0.LVLMODE is 0; however, it is recommended to set
input level of the external pin is not retained.
ICR0.LVLMODE to 1 by setting the interrupt control register 0 (ICR0) by the initialization
routine.
Features
Section 10 Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 263 of 1658
10. Interrupt Controller (INTC)
REJ09B0261-0100