r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 654

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r8a77850anbg

Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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13. PCI Controller (PCIC)
(24) PCI Cache Snoop Control Register 0 (PCICSCR0)
An external PCI device can access memory of this LSI via the PCIC. When an PCI device
accesses a cacheable area, the PCIC can issue cache snoop commands to the on-chip caches. This
register can specify the function that uses PCICSAR0. For details, see section 13.4.4 (7), Cache
Coherency.
Rev.1.00 Jan. 10, 2008 Page 624 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 5
4 to 2
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
Bit:
Bit:
Bit Name
RANGE
31
15
R
R
0
0
30
14
R
R
0
0
Initial
Value
All 0
All 0
29
13
R
R
0
0
28
12
R
R
0
0
R/W
SH: R
PCI: —
SH: R/W
PCI: —
27
11
R
R
0
0
26
10
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Address Range to be Compared
These bits specify the address range of PCICSAR0 to
be compared.
000: Compared with PCICSAR0.CADR[31:12] (4 kbytes)
001: Compared with PCICSAR0.CADR[31:16] (64 kbytes)
010: Compared with PCICSAR0.CADR[31:20] (1 Mbyte)
011: Compared with PCICSAR0.CADR[31:24] (16 Mbytes)
100: Compared with PCICSAR0.CADR[31:25] (32 Mbytes)
101: Compared with PCICSAR0.CADR[31:26] (64 Mbytes)
110: Compared with PCICSAR0.CADR[31:27] (128 Mbytes)
111: Compared with PCICSAR0.CADR[31:28] (256 Mbytes)
Valid only when PCICSCR0.SNPMD = 10 or 11.
25
R
R
0
9
0
24
R
R
0
8
0
23
R
R
0
7
0
22
R
R
0
6
0
21
R
R
0
5
0
R/W
20
R
0
4
0
RANGE
R/W
19
R
0
3
0
R/W
18
R
0
2
0
R/W
17
R
0
1
0
SNPMD
R/W
16
R
0
0
0

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