r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 800

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

16. Watchdog Timer and Reset (WDT)
(2)
• Requesting sources
• Branch address: H'A000 0000
• Operation until branching
Rev.1.00 Jan. 10, 2008 Page 770 of 1658
REJ09B0261-0100
⎯ A general exception other than a user break while the BL bit in SR is set to 1.
⎯ WDTCNT overflow when both the WT/IT and RSTS bits in WDTCSR are set to 1
The exception code H'020 is set in EXPEVT. After initializing VBR and SR, the processing
branches by setting PC = H'A000 0000.
During initialization, the VBR register is rest to H'0000 0000. The SR register is initialized
such that the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt
mask level bits (IMASK3 to IMASK0) are set to B'1111.
Then, the CPU and peripheral modules are initialized. For details, refer to the register
descriptions in the corresponding sections.
Manual Reset
Manual_reset()
{
}
EXPEVT = H'0000 0020;
VBR = H'0000 0000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(Manual);
PC = H'A000 0000;