r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1170

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

22. Serial I/O with FIFO (SIOF)
(2)
Figure 22.10 shows an example of settings and operation for master mode reception.
Rev.1.00 Jan. 10, 2008 Page 1140 of 1658
REJ09B0261-0100
Reception in Master Mode
No.
1
2
3
4
5
6
7
8
Store SIOF_RXD receive data in SIRDR
Set the FSE and RXE bits in SICTR to 1
synchronously with SIOF_SYNC
Clear the RXE bit in SICTR to 0
Set the SCKE bit in SICTR to 1
Figure 22.10 Example of Receive Operation in Master Mode
Set SIMDR, SISCR, SITDAR,
SIRDAR, SICDAR, SITCR,
Start SIOF_SCK output
Transfer ended?
Read SIRDR
and SIFCTR
RDREQ = 1
Flowchart
Start
End
Yes
Yes
No
No
Set operating mode, serial clock, slot
positions for transmit/receive data, slot
position for control data, and FIFO
request threshold value
Set operation start for baud rate generator
Set the start for frame synchronous signal
output and enable reception
Read receive data
Set to disable reception
SIOF Settings
Output serial clock
Output frame
synchronous signal
Issue receive transfer
request according to
the receive FIFO
threshold value
Receive
End reception
SIOF Operation