r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 241

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

This LSI has an on-chip 32-Kbyte instruction cache (IC) for instructions and an on-chip 32-Kbyte
operand cache (OC) for data.
8.1
The features of the cache are given in table 8.1.
This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external
memory. The features of the store queues are given in table 8.2.
Table 8.1
Table 8.2
The operand cache of this LSI is 4-way set associative, each may comprising 256 cache lines.
Figure 8.1 shows the configuration of the operand cache.
The instruction cache is 4-way set-associative, each way comprising 256 cache lines. Figure 8.2
shows the configuration of the instruction cache.
Item
Capacity
Type
Line size
Entries
Write method
Replacement method
Item
Capacity
Addresses
Write
Write-back
Access right
Features
Cache Features
Store Queue Features
Instruction Cache
32-Kbyte cache
4-way set-associative, virtual
address index/physical address tag
32 bytes
256 entries/way
⎯
LRU (least-recently-used) algorithm LRU (least-recently-used) algorithm
Store Queues
32 bytes × 2
H'E000 0000 to H'E3FF FFFF
Store instruction (1-cycle write)
Prefetch instruction (PREF instruction)
When MMU is disabled: Determined by SQMD bit in MMUCR
When MMU is enabled: Determined by PR for each page
Section 8 Caches
Rev.1.00 Jan. 10, 2008 Page 211 of 1658
Operand Cache
32-Kbyte cache
4-way set-associative, virtual
address index/physical address tag
32 bytes
256 entries/way
Copy-back/write-through selectable
REJ09B0261-0100
8. Caches