r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 935

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

19.3.38 Plane n Display Area Start Address 0 Register (PnDSA0R) (n = 1 to 6)
The plane n display area start address 0 registers (PnDSA0R, n = 1 to 6) set the memory area in
frame buffer 0 for plane n. The value is retained during power-on reset and manual reset.
Internal update:
Internal update:
Bit
31 to 4
3 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
PnDSA0
⎯
R/W
R/W
31
15
—
—
O
O
R/W
R/W
30
14
—
—
O
O
Initial
Value
Undefined R/W
All 0
R/W
R/W
29
—
13
—
O
O
R/W
R/W
28
12
—
—
O
O
R/W
R
R/W
R/W
27
11
—
—
O
O
Internal
Update
Yes
⎯
R/W
R/W
26
10
—
—
O
O
PnDSA0
R/W
R/W
25
—
—
O
O
9
Description
Plane n Display Area Start Address 0
To enable the 31 to 29 bits, the DSAE bit in
DEFR should be set to 1.
In the initial state the bits are not enabled, and
are fixed at 0.
When the buffer mode for plane n is manual
display change mode or auto display change
mode, the buffer is used as frame buffer 0.
Note: In 32-bit address extended mode, when
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
R/W
24
—
—
O
O
8
PnDSA0
the 31 to 29 bits in this register are
disabled, of the lower 29 bits in a specified
32-bit physical address, a 25-bit address
(A28 to A4) is specified in the 28 to 4 bits.
R/W
R/W
23
—
—
O
O
7
Rev.1.00 Jan. 10, 2008 Page 905 of 1658
R/W
R/W
22
—
—
O
O
6
R/W
R/W
21
—
—
O
O
5
R/W
R/W
20
—
—
O
O
4
R/W
19. Display Unit (DU)
19
—
—
O
R
3
0
REJ09B0261-0100
R/W
18
—
—
O
R
2
0
R/W
17
—
—
O
R
1
0
R/W
16
—
—
O
R
0
0