r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 638

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 608 of 1658
REJ09B0261-0100
Bit
11
10 to 4
3
2
1
0
Bit Name
⎯
MBTOI
TAI
MAI
RDPEI
WDPEI
Initial
Value
0
All 0
0
0
0
0
R/W
SH: R/WC
PCI: R
SH: R
PCI: R
SH: R/WC
PCI: R
SH: R/WC
PCI: R
SH: R/WC
PCI: R
SH: R/WC
PCI: R
Description
Master Bus Time-Out Interrupt
An interrupt is detected when IRDY is not asserted
within 8 clock cycles during data transfer.
0: A master bus timeout interrupt was not generated
1: A master bus timeout interrupt was generated
Reserved
These bits are always read as 0. The write value
should always be 0.
Target-Abort Interrupt
Indicates that a transaction was terminated by a target
abort when a device other than the PCIC is a bus
master.
0: A target abort interrupt was not generated
1: A target abort interrupt was generated
Master-Abort Interrupt
Indicates that a transaction was terminated by a
master abort when a device other than the PCIC is a
bus master.
0: A master abort interrupt was not generated
1: A master abort interrupt was generated
Read Parity Error Interrupt
PERR assertion was detected during data read when
a device other than the PCIC is a bus master.
0: A read parity error interrupt was not generated
1: A read parity error interrupt was generated
Write Parity Error Interrupt
PERR assertion was detected during data write when
a device other than the PCIC is a bus master.
0: A write data parity error interrupt was not generated
1: A write data parity error interrupt was generated