r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 707

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r8a77850anbg

Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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14.3.3
DAR are 32-bit readable/writable registers that specify the destination address of a DMA transfer.
During a DMA transfer, these registers indicate the destination address of the next transfer.
A word or longword boundary address should be specified when a word or longword transfer is
performed respectively. A 16-byte or 32-byte boundary value should be specified when a 16-byte
or 32-byte transfer is performed respectively.
In 29-bit address mode, the source address is changed as follows before it is output.
• The upper three bits are output as 000 when bits 31 to 29 are not 111 and areas 0 to 6 are used.
• The upper three bits are output as 111 when bits 31 to 29 are not 111 and area 7 is used.
• The written address is output as it is when bits 31 to 29 are 111.
In 32-bit address mode, the written address is output as it is.
The initial value of DAR is undefined.
Initial value:
Initial value:
R/W:
R/W:
BIt:
BIt:
DMA Destination Address Registers 0 to 11 (DAR0 to DAR11)
R/W
R/W
31
15
R/W
R/W
30
14
R/W
R/W
29
13
R/W
R/W
28
12
R/W
R/W
27
11
R/W
R/W
26
10
R/W
R/W
25
9
R/W
R/W
24
8
R/W
R/W
23
7
14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 677 of 1658
R/W
R/W
22
6
R/W
R/W
21
5
R/W
R/W
20
4
R/W
R/W
19
3
REJ09B0261-0100
R/W
R/W
18
2
R/W
R/W
17
1
R/W
R/W
16
0

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