r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1137

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Bit
8
7 to 2
1
0
Bit Name
RXE
⎯
TXRST
RXRST
All 0
0
0
Initial
Value
0
R
R/W
R/W
R/W
R/W
Description
Receive Enable
0: Disables data reception from SIOF_RXD
1: Enables data reception from SIOF_RXD
•
•
•
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit Reset
0: Does not reset transmit operation
1: Resets transmit operation
•
•
Receive Reset
0: Does not reset receive operation
1: Resets receive operation
•
•
This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOF_SYNC signal).
When the 1 setting for this bit becomes valid, the
SIOF begins the reception of data from the
SIOF_RXD pin. When receive data is stored in the
receive FIFO, the SIOF issues a reception transfer
request according to the setting of the RFWM bit in
SIFCTR.
This bit is initialized by a receive reset.
This bit setting becomes valid immediately. For
details on initialization, see section 22.4.7 (5),
Transmit/Receive Reset.
This bit is automatically cleared by SIOF after
completes a reset, to be always read as 0.
This bit setting becomes valid immediately. For
details on initialization, see section 22.4.7 (5),
Transmit/Receive Reset.
This bit is automatically cleared by SIOF after
completes a reset, to be always read as 0.
Rev.1.00 Jan. 10, 2008 Page 1107 of 1658
22. Serial I/O with FIFO (SIOF)
REJ09B0261-0100