r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 223

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r8a77850anbg

Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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7.7.3
In TLB extended mode the names of the data arrays have been changed from ITLB data array to
ITLB data array 1, ITLB data array 2 is added, and the EPR and ESZ bits are accessible. In TLB
extended mode, the PR and SZ bits of ITLB data array 1 are reserved and 0 should be specified as
the write value for these bits. In addition, when a write to ITLB data array 1 is performed, a write
to ITLB data array 2 of the same entry should always be performed.
In TLB compatible mode (MMUCR.ME = 0), ITLB data array 2 cannot be accessed. Operation if
they are accessed is not guaranteed.
(1)
In TLB extended mode, bits 7, 6, and 4 in the data field, which correspond to the PR and SZ bits
in compatible mode, are reserved. Specify 0 as the write value for these bits.
ITLB Data Array 1
ITLB Data Array (TLB Extended Mode)
Figure 7.20 Memory-Mapped ITLB Data Array 1 (TLB Extended Mode)
Address field
Data field
Legend:
PPN:
V:
E:
*:
31
31
1 1 1 1 0 0 1 1 0
Physical page number
Validity bit
Entry
Don't care
29 28
23 22
*
*
*
PPN
C:
SH:
*
:
* *
Cacheability bit
Share status bit
Reserved bits
(write value should be 0,
and read value is undefined)
* * * * * * *
Rev.1.00 Jan. 10, 2008 Page 193 of 1658
10 9 8 7
10 9
7. Memory Management Unit (MMU)
E
V
8 7
* * * * * *
4 3
C
2 1
2 1 0
REJ09B0261-0100
0
SH
0
0

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