r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 526

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 496 of 1658
REJ09B0261-0100
Bit
20 to 16 TRC4 to
15 to 12 ⎯
Bit Name
TRC0
Initial
Value
0 0100
All 0
R/W
R/W
R
Description
tRC (ACT-ACT/REF period) Setting Bits
These bits set the constraint for the minimum time from
ACT command to ACT command (in the same bank)/
REF command. These bits should be set according to
the SDRAM specifications. The number of cycles is the
number of DDR clock cycles.
00000: Setting prohibit (If specified, correct operation
00011: Setting prohibit (If specified, correct operation
00100: 5 cycles
00101: 6 cycles
10010: 19 cycles
10011: Setting prohibit (If specified, correct operation
11111: Setting prohibit (If specified, correct operation
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
:
:
:
cannot be guaranteed.)
cannot be guaranteed.)
cannot be guaranteed.)
cannot be guaranteed.)