r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1134

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

22. Serial I/O with FIFO (SIOF)
22.3.1
SIMDR is a 16-bit readable/writable register that sets the SIOF operating mode.
Rev.1.00 Jan. 10, 2008 Page 1104 of 1658
REJ09B0261-0100
Initial value:
Bit
15, 14
13
12
11 to 8
R/W:
BIt:
Mode Register (SIMDR)
Bit Name
TRMD[1:0]
SYNCAT
REDG
FL[3:0]
R/W
TRMD[1:0]
15
1
R/W
14
0
R/W
SYN
CAT
13
0
Initial
Value
10
0
0
0000
REDG
R/W
12
0
R/W
R/W
R/W
R/W
R/W
R/W
11
0
R/W
10
0
FL[3:0]
Description
Transfer Mode 1, 0
These bits select transfer mode shown in table 22.4.
00: Slave mode 1
01: Slave mode 2
10: Master mode 1
11: Master mode 2
SIOF_SYNC Pin Valid Timing
Indicates the position of the SIOF_SYNC signal to be
output as a synchronous pulse.
0: At the start bit data of frame
1: At the last bit data of slot
Receive Data Sampling Edge
0: The SIOF_RXD signal is sampled at the falling edge
1: The SIOF_RXD signal is sampled at the rising edge
Note: The timing to transmit the SIOF_TXD signal is at
Frame Length 3 to 0
These bits specify the flame length of transfer data
format. For the correspondence among setting values,
data length, and frame length, see table 22.7.
R/W
of SIOF_SCK
of SIOF_SCK
9
0
R/W
the opposite edge of the timing that samples the
SIOF_RXD. This bit is valid only in master
mode.
8
0
TXDIZ
R/W
7
0
RCIM
R/W
6
0
R/W
CAC
SYN
5
0
R/W
SYN
CDL
4
0
—
R
3
0
—
R
2
0
—
R
1
0
—
R
0
0