r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 278

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r8a77850anbg

Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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9. On-Chip Memory
9.2.2
When MMUCR.AT = 0 or RAMCR.RP = 0, the LSA0 specifies the transfer source physical
address for block transfer to page 0A or 0B of the OL memory.
Rev.1.00 Jan. 10, 2008 Page 248 of 1658
REJ09B0261-0100
Bit
6
5
4 to 0
Bit
31 to 29 —
28 to 10 L0SADR
9 to 6
Initial value :
Initial value :
R/W:
R/W:
Bit :
Bit :
OL memory Transfer Source Address Register 0 (LSA0)
Bit Name
OC2W
ICWPD
Bit Name
R/W
31
15
R
0
R/W
30
14
R
0
R/W
29
13
Initial
Value
0
0
All 0
L0DADR
Initial
Value
All 0
Undefined R/W
All 0
R
0
R/W
R/W
28
12
R/W
R/W
27
11
R/W
R/W
R/W
R
R/W
R
R
R/W
R/W
26
10
Description
For further details, refer to section 8.3.6, OC Two-Way
Mode.
IC Way Prediction Disable
For further details, refer to section 8.4.4, Instruction
Cache Way Prediction Operation.
For read/write in these bits, refer to General
Precautions on Handling of Product.
Description
Reserved
For read/write in these bits, refer General Precautions
on Handling of Product.
When MMUCR.AT = 0 or RAMCR.RP = 0, these bits
specify the transfer source physical address for block
transfer to page 0A or 0B in the OL memory.
Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.
OC Two-Way Mode
Reserved
OL memory Page 0 Block Transfer Source Address
R/W
25
R
9
0
R/W
24
R
8
0
R/W
23
R
7
0
L0DADR
R/W
22
R
6
0
R/W
R/W
21
5
R/W
R/W
20
4
R/W
R/W
19
3
L0DSZ
R/W
R/W
18
2
R/W
R/W
17
1
R/W
R/W
16
0

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