r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1212

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

24. Multimedia Card Interface (MMCIF)
Rev.1.00 Jan. 10, 2008 Page 1182 of 1658
REJ09B0261-0100
Bit
5
4
3
2
1
Bit Name
FIFO_EMPTY
CWRE
DTBUSY
DTBUSY_TU Undefined
—
Initial
Value
0
0
0
0
R/W
R
R
R
R
R
Description
FIFO Empty
This bit is set to 1 when the FIFO becomes empty while
data is being sent to the card, and cleared to 0 when
DATA_EN is set to 1 or the command sequence is
completed.
Indicates whether the FIFO holds data or not.
0: The FIFO includes data.
1: The FIFO is empty.
Command Register Write Enable
Indicates whether the CMDR command is being
transmitted or has been transmitted.
0: The CMDR command has been transmitted, or the
1: The CMDR command is waiting for transmission or is
Data Busy
Indicates command execution status. Indicates that the
card is in the busy state after the command sequence
of a command without data transfer which includes the
busy state in the response, or a command with write
data has been ended.
0: Idle state waiting for a command, or command
1: Card is in the data busy state after command
Data Busy Pin Status
Indicates the MMCDAT pin level. By reading this bit, the
MMCDAT level can be monitored.
0: A low level is input to the MMCDAT pin.
1: A high level is input to the MMCDAT pin.
Reserved
This bit is always read as 0. The write value should
always be 0.
CMDSTART bit in CMDSTRT has not been set yet,
so the new command can be written.
being transmitted. If a new command is written, a
malfunction will result.
sequence execution in progress
sequence termination.