r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1034

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

20. Graphics Data Translation Accelerator (GDTA)
20.3.23 MC Frame Width Setting Register (MCWR)
MCWR is in the MC register block and sets the input frame width in pixel units.
Notes: 1. MC processing is prohibited when the setting is 0.
Rev.1.00 Jan. 10, 2008 Page 1004 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
2 to 0
Bit
31 to 12 ⎯
11 to 0
R/W:
R/W:
BIt:
BIt:
2. Addition is performed taking that 1 pixel = 1 byte.
3. MCWR (bytes) + MCYPR (bytes) should be 16 bytes x n (n: an integer greater than 0)
4. MCWR (bytes)/2 + MCUVPR (bytes) should be 8 bytes x n (n: an integer greater than
5. MCWR (bytes)/2: Shifts the MCWR setting one bit to the right. (When the setting is odd,
Bit Name
MC_CFS
Bit Name
MC_W
0)
the bit 0 setting is discarded.)
31
15
⎯
⎯
⎯
⎯
0
0
30
⎯
⎯
14
⎯
⎯
0
0
29
⎯
⎯
13
⎯
⎯
0
0
Initial
Value
All 0
Initial
Value
All 0
All 0
28
12
⎯
⎯
⎯
⎯
0
0
R/W
R/W
R
R/W
⎯
R/W
27
11
⎯
⎯
0
0
R/W
26
10
⎯
⎯
0
0
Description
Command pointer status display
000: MCCF command parameter 1 setting wait state
001: MCCF command parameter 2 setting wait state
010: MCCF command parameter 3 setting wait state
011: MCCF command parameter 4 setting wait state
100: MCCF command parameter 5 setting wait state
101: MCCF command parameter 6 setting wait state
110: MCCF command parameter 7 setting wait state
111: MCCF command parameter 8 setting wait state
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Frame width setting
Should be set by the number of pixels.
R/W
25
⎯
⎯
0
9
0
R/W
24
⎯
⎯
0
8
0
R/W
23
⎯
⎯
0
7
0
R/W
22
⎯
⎯
0
6
0
MC_W
R/W
21
⎯
⎯
0
5
0
R/W
20
⎯
⎯
0
4
0
R/W
19
⎯
⎯
0
3
0
R/W
18
⎯
⎯
0
2
0
R/W
17
⎯
⎯
0
1
0
R/W
16
⎯
⎯
0
0
0