r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1090

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

21. Serial Communication Interface with FIFO (SCIF)
Legend:
etu:
Notes: 1. Only 0 can be written to clear the flag.
Rev.1.00 Jan. 10, 2008 Page 1060 of 1658
REJ09B0261-0100
Bit
0
Elementary time unit (time for transfer of 1 bit)
2. In 2-stop bit mode, only the first stop bit is checked for a value of 1; the second stop bit
3. As SCFTDR is a 64-byte FIFO register, the maximum number of bytes that can be
4. When a break is detected, the receive data (H'00) following detection is not transferred
5. SCFRDR is a 64-byte FIFO register. When RDF = 1, at least the receive trigger setting
6. Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format
Bit Name
DR
is not checked.
written when TDFE = 1 is 64 − (transmit trigger setting count). Data written in excess of
this is ignored. The upper bits of SCTFDR indicate the number of data bytes transmitted
to SCFTDR.
to SCFRDR. When the break ends and the receive signal returns to mark 1, receive
data transfer is resumed.
count of data bytes can be read. If all the data in SCFRDR is read and another read is
performed, the data value is undefined. The number of receive data bytes in SCFRDR
is indicated by SCRFDR.
Initial
Value
0
R/W
R/W*
1
Description
Receive Data Ready
In asynchronous mode, indicates that there are fewer
than the receive trigger setting count of data bytes in
SCFRDR, and no further data has arrived for at least
15 etu after the stop bit of the last data received. This is
not set when using clocked synchronous mode.
0: Reception is in progress or has ended normally and
[Clearing conditions]
•
•
•
1: No further receive data has arrived
[Setting condition]
•
there is no receive data left in SCFRDR
Power-on reset or manual reset
When all the receive data in SCFRDR has been
read after reading DR = 1, and 0 is written to DR
When all the receive data in SCFRDR has been
read by the DMAC
When SCFRDR contains fewer than the receive
trigger setting count of receive data bytes, and no
further data has arrived for at least 15 etu after the
stop bit of the last data received*
6