r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 994

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

19. Display Unit (DU)
• Display in interlaced method
Rev.1.00 Jan. 10, 2008 Page 964 of 1658
REJ09B0261-0100
At every scan period VC of the input video signal, even lines and odd lines are switched and
displayed in alternation, and a single screen (one frame) is combined and displayed (with the
afterimage of the preceding VC) with a period of 2VC. This is the normal TV input method.
HSYNC
2. Display in interlaced sync & video mode
1. Display in interlaced sync mode
· The first field is an odd field (the ODDF pin is low)
· The second field is an even field (the ODDF pin is high)
When one frame is configured as shown below,
clear the ODEV bit to 0.
· The first field is an odd field (the ODDF pin is low)
· The second field is an even field (the ODDF pin is high)
When one frame is configured as shown below,
clear the ODEV bit to 0.
HSYNC
Odd filed
Even field
Odd filed
Even field
238
239
238
239
0
1
2
3
0
1
2
3
477
479
476
478
1
3
5
7
0
2
4
6
Figure 19.18 Display in Interlaced Method
VSYNC
VSYNC
ODDF
ODDF
HSYNC
HSYNC
· The first field is an even field (the ODDF pin is high)
· The second field is an odd field (the ODDF pin is low)
· The first field is an even field (the ODDF pin is high)
· The second field is an odd field (the ODDF pin is low)
When one frame is configured as shown below,
set the ODEV bit to 1.
When one frame is configured as shown below,
set the ODEV bit to 1.
Even field
Odd filed
Even field
Odd filed
476
478
477
479
0
2
4
6
1
3
5
7
238
239
238
239
0
1
2
3
0
1
2
3
VSYNC
VSYNC
ODDF
ODDF