r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 274

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

9. On-Chip Memory
(2)
• Capacity
• Page
• Memory map
Table 9.2
• Ports
• Priority
(3)
• Capacity
• Access method
• Memory map
Rev.1.00 Jan. 10, 2008 Page 244 of 1658
REJ09B0261-0100
Page
Page 0
Page 1
The IL memory in this LSI is 8 Kbytes.
The IL memory is divided into two pages (pages 0 and 1).
The IL memory is allocated to the addresses shown in table 9.2 in both the virtual address
space and the physical address space.
The page has three independent read/write ports and is connected to the SuperHyway bus, the
cache/RAM internal bus, and the instruction bus. The instruction bus is used when the IL
memory is accessed through instruction fetch. The cache/RAM internal bus is used when the
IL memory is accessed through operand access. The SuperHyway bus is used for IL memory
access from the SuperHyway bus master module.
In the event of simultaneous accesses to the same page from different buses, the access
requests are processed according to priority. The priority order is: SuperHyway bus >
cache/RAM internal bus > instruction bus.
The U memory in this LSI is 128 Kbytes.
Instruction fetch and operand write access are performed via the cache/RAM internal bus.
Operand read access is optimized for sequential operand access by using the read buffer.
The U memory is allocated to the addresses shown in table 9.3 in both the virtual address
space and the physical address space.
IL Memory
U Memory
IL Memory Addresses
Memory Address
H'E520 0000 to H'E520 0FFF
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