r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 90

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

3. Instruction Set
Rev.1.00 Jan. 10, 2008 Page 60 of 1658
REJ09B0261-0100
Instruction
LDC
LDC
LDC
LDC
LDC.L
LDC.L
LDC.L
LDC.L
LDC.L
LDC.L
LDC.L
LDC.L
LDS
LDS
LDS
LDS.L
LDS.L
LDS.L
LDTLB
MOVCA.L
NOP
OCBI
OCBP
OCBWB
PREF
PREFI
RTE
Rm,SSR
Rm,SPC
Rm,DBR
Rm,Rn_BANK Rm → Rn_BANK (n = 0 to 7) 0100mmmm1nnn1110
@Rm+,SR
@Rm+,GBR
@Rm+,VBR
@Rm+,SGR
@Rm+,SSR
@Rm+,SPC
@Rm+,DBR
@Rm+,Rn_
BANK
Rm,MACH
Rm,MACL
Rm,PR
@Rm+,MACH (Rm) → MACH, Rm + 4 →
@Rm+,MACL
@Rm+,PR
R0,@Rn
@Rn
@Rn
@Rn
@Rn
@Rn
(Rm) → SR, Rm + 4 → Rm
(Rm) → GBR, Rm + 4 → Rm 0100mmmm00010111
(Rm) → VBR, Rm + 4 → Rm 0100mmmm00100111
(Rm) → SGR, Rm + 4 → Rm 0100mmmm00110110
(Rm) → SSR, Rm + 4 → Rm 0100mmmm00110111
(Rm) → SPC, Rm + 4 → Rm 0100mmmm01000111
(Rm) → DBR, Rm + 4 → Rm 0100mmmm11110110
(Rm) → MACL, Rm + 4 →
(Rm) → PR, Rm + 4 → Rm
Writes back operand cache
(Rn) → operand cache
Reads 32-byte instruction
Operation
Rm → SSR
Rm → SPC
Rm → DBR
(Rm) → Rn_BANK,
Rm + 4 → Rm
Rm → MACH
Rm → MACL
Rm → PR
Rm
Rm
PTEH/PTEL (/PTEA) → TLB 0000000000111000
R0 → (Rn) (without fetching
cache block)
No operation
Invalidates operand cache
block
Writes back and invalidates
operand cache block
block
block into instruction cache
Delayed branch, SSR/SPC
→ SR/PC
Instruction Code
0100mmmm00111110
0100mmmm01001110
0100mmmm11111010
0100mmmm00000111
0100mmmm1nnn0111
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00000110
0100mmmm00010110
0100mmmm00100110
0000nnnn11000011
0000000000001001
0000nnnn10010011
0000nnnn10100011
0000nnnn10110011
0000nnnn10000011
0000nnnn11010011
0000000000101011
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