r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 186

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

7. Memory Management Unit (MMU)
7.2.4
After an MMU exception or address error exception occurs, the virtual address at which the
exception occurred is stored. The contents of this register can be changed by software.
7.2.5
The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should
be performed by a program in the P1 or P2 area.
After MMUCR has been updated, execute one of the following three methods before an access
(including an instruction fetch) to the P0, P3, U0, or store queue area is performed.
1. Execute a branch using the RTE instruction. In this case, the branch destination may be the P0,
2. Execute the ICBI instruction for any address (including non-cacheable area).
3. If the R2 bit in IRMCR is 0 (initial value) before updating MMUCR, the specific instruction
Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is
recommended that the method 1 or 2 should be used for being compatible with the future SuperH
Series.
MMUCR contents can be changed by software. However, the LRUI and URC bits may also be
updated by hardware.
Rev.1.00 Jan. 10, 2008 Page 156 of 1658
REJ09B0261-0100
Initial value:
Initial value:
P3, or U0 area.
does not need to be executed. However, note that the CPU processing performance will be
lowered because the instruction fetch is performed again for the next instruction after
MMUCR has been updated.
R/W:
R/W:
Bit:
Bit:
TLB Exception Address Register (TEA)
MMU Control Register (MMUCR)
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
31
15
R/W R/W R/W R/W
TEA
TEA
30
14
29
13
Virtual address at which MMU exception or address error occurred
Virtual address at which MMU exception or address error occurred
28
12
27
11
R/W
26
10
R/W
25
9
R/W
24
8
R/W R/W R/W R/W R/W R/W R/W R/W
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0