r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1188

Manufacturer Part Number

r8a77850anbg

Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family

Manufacturer

Renesas Electronics Corporation.

Manufacturer

BOSTOCK HK LIMITED

Part Number:

r8a77850anbgV

Manufacturer:

Renesas Electronics America

23. Serial Peripheral Interface (HSPI)

SPSR is a 32-bit readable/writable register. Through the status flags in SPSR, it can be confirmed

whether or not the system is correctly operating. If the ROIE bit in SPSCR is set to 1, an interrupt

request is generated due to the occurrence of the receive buffer overrun error or the warning of the

receive buffer overrun error. When the TFIE bit in SPSCR is set to 1, an interrupt request is

generated by the transmit complete status flag. If the appropriate enable bit in SPSCR is set to 1,

an interrupt request is generated due to the receive FIFO halfway, receive FIFO full, transmit

FIFO empty, or transmit FIFO halfway flag. If the RNIE bit in SPSCR is set to 1, an interrupt

request is generated when the receive FIFO is not empty.

Rev.1.00 Jan. 10, 2008 Page 1158 of 1658

REJ09B0261-0100

Initial value:

Status Register (SPSR)

These bits are always read as an undefined value. The

write value should always be 0.

Transmit FIFO Full Flag

This status flag is enabled only in FIFO mode. The flag

is set to 1 when the transmit FIFO is full of bytes for

transmission and cannot accept any more. It is cleared

to 0 when data is transmitted from the transmit FIFO to

the HSPI bus.

Transmit FIFO Halfway Flag

This status flag is enabled only in FIFO mode. The flag

is set to 1 when the transmit FIFO reaches the halfway

point, that is, it has four bytes of data and free space for

four bytes of data. It is cleared to 0 when more data is

written to the transmit FIFO. It remains set to 1 until

cleared to 0 even if data stored in the FIFO becomes

less than four bytes (halfway point).

If TXHA = 1 and THIE = 1, an interrupt is generated.