r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 177

Manufacturer Part Number

r8a77850anbg

Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family

Manufacturer

Renesas Electronics Corporation.

Manufacturer

BOSTOCK HK LIMITED

Part Number:

r8a77850anbgV

Manufacturer:

Renesas Electronics America

The P0, P3, and U0 areas allow address translation using the TLB and access using the cache.

When the MMU is disabled, replacing the upper 3 bits of an address with 0s gives the

corresponding physical address. Whether or not the cache is used is determined by the CCR

setting. When the cache is used, switching between the copy-back method and the write-

through method for write accesses is specified by the WT bit in CCR.

When the MMU is enabled, these areas can be mapped onto any physical address space in 1-,

4-, 64-Kbyte, or 1-Mbyte page units in TLB compatible mode and in 1-, 4-, 8-, 64, 256-Kbyte,

1-, 4-, or 64-Mbyte page units in TLB extended mode using the TLB. When CCR is in the

cache enabled state and the C bit for the corresponding page of the TLB entry is 1, accesses

can be performed using the cache. When the cache is used, switching between the copy-back

method and the write-through method for write accesses is specified by the WT bit of the TLB

When the P0, P3, and U0 areas are mapped onto the control register area which is allocated in

the area 7 in physical address space by means of the TLB, the C bit for the corresponding page

must be cleared to 0.

P0, P3, and U0 Areas

Address translation not possible

Address translation possible

Privileged mode

Non-cacheable

Figure 7.3 Virtual Address Space (AT in MMUCR = 1)

address space

Address translation possible

Rev.1.00 Jan. 10, 2008 Page 147 of 1658

On-chip memory area

Store queue area

Address error

7. Memory Management Unit (MMU)

REJ09B0261-0100