r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 530

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

12. DDR2-SDRAM Interface (DBSC2)
12.4.9
The SDRAM refresh control register 1 (DBRFCNT1) is a readable/writable register. It is
initialized only upon power-on reset.
Rev.1.00 Jan. 10, 2008 Page 500 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
0
Bit
31 to 13 ⎯
R/W:
R/W:
BIt:
BIt:
SDRAM Refresh Control Register 1 (DBRFCNT1)
Bit Name
SRFEN
Bit Name
31
15
⎯
⎯
R
R
0
0
30
⎯
14
⎯
R
R
0
0
Initial
Value
0
29
⎯
13
⎯
Initial
Value
All 0
R
R
0
0
TREFI12
R/W
28
12
⎯
R
0
0
TREFI11
R/W
27
11
⎯
R
0
0
R/W
R/W
R/W
R
TREFI10
R/W
26
10
⎯
R
0
0
Description
Self-Refresh Mode Bit
Performs transition to or cancellation of self-refresh
mode. By writing 1, a transition is made to self-refresh.
By writing 0, self-refresh mode is cancelled. For details
on transition to or cancellation of self-refresh, refer to
section 12.5.4, Self-Refresh Operation.
0: Cancels self-refresh.
1: Makes a transition to self-refresh.
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
TREFI9
R/W
25
⎯
R
0
9
1
TREFI8
R/W
24
⎯
R
0
8
0
TREFI7
R/W
23
⎯
R
0
7
0
TREFI6
R/W
22
⎯
R
0
6
0
TREFI5
R/W
21
⎯
R
0
5
0
TREFI4
R/W
20
⎯
R
0
4
0
TREFI3
R/W
19
⎯
R
0
3
0
TREFI2
R/W
18
⎯
R
0
2
0
TREFI1
R/W
17
⎯
R
0
1
0
TREFI0
R/W
16
⎯
R
0
0
0