r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1191

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

23.3.3
SPSCR is a 32-bit readable/writable register that enables or disables interrupts or FIFO mode,
selects either LSB first or MSB first in transmitting/receiving data, and master or slave mode.
If any of the FFEN, LMSB, CSA, or MASL bit values are changed, the module will undergo a
software reset.
Initial value:
Initial value:
Bit
31 to 14 ⎯
13
12
11
10
9
R/W:
R/W:
Bit:
Bit:
System Control Register (SPSCR)
Bit Name
TEIE
THIE
RNIE
RHIE
RFIE
31
15
—
—
R
R
0
0
30
14
—
—
R
R
0
0
TEIE
R/W
Initial
Value
All 0
0
0
0
0
0
29
13
—
R
0
0
THIE
R/W
28
—
12
R
0
0
RNIE
R/W
27
—
11
R/W
R
R/W
R
R/W
R/W
R/W
R/W
0
0
RHIE
R/W
26
10
—
R
0
0
Description
Reserved
These bits are always read as an undefined value. The
write value should always be 0.
Transmit FIFO Empty Interrupt Enable
0: Transmit FIFO empty interrupt disabled
1: Transmit FIFO empty interrupt enabled
Transmit FIFO Halfway Interrupt Enable
0: Transmit FIFO halfway interrupt disabled
1: Transmit FIFO halfway interrupt enabled
Receive FIFO Not Empty Interrupt Enable
0: Receive FIFO not empty interrupt disabled
1: Receive FIFO not empty interrupt enabled
Receive FIFO Halfway Interrupt Enable
0: Receive FIFO halfway interrupt disabled
1: Receive FIFO halfway interrupt enabled
Receive FIFO Full Interrupt Enable
0: Receive FIFO full interrupt disabled
1: Receive FIFO full interrupt enabled
RFIE
R/W
25
—
R
0
9
0
FFEN
R/W
24
—
R
0
8
0
LMSB
R/W
23
—
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 1161 of 1658
CSV
R/W
22
—
R
0
6
1
23. Serial Peripheral Interface (HSPI)
CSA
R/W
21
—
R
0
5
0
TFIE
R/W
20
—
R
0
4
0
ROIE
R/W
19
—
R
0
3
0
REJ09B0261-0100
RXDE
R/W
18
—
R
0
2
0
TXDE
R/W
17
—
R
0
1
0
MASL
R/W
16
—
R
0
0
0