r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1635

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r8a77850anbg

Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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32.3.10 H-UDI Module Signal Timing
Table 32.15 H-UDI Module Signal Timing
Conditions: V
Notes: 1. During a boundary scan, t
Item
Input clock cycle
Input clock pulse width (high)
Input clock pulse width (low)
Input clock rise time
Input clock fall time
ASEBRK setup time
ASEBRK hold time
TDI/TMS setup time
TDI/TMS hold time
TDO data delay time
ASE-PINBRK pulse width
2. t
3. t
0.1 μs.
cyc
Pcyc
is the period of one CKIO clock cycle.
is the period of one peripheral clock (Pck) cycle.
DDQ
= 3.0 to 3.6 V, V
Note: When the clock is input from the TCK pin.
1/2V
DDQ
Figure 32.44 TCK Input Timing
DD
= 1.1 V, T
TCKcyc
V
IH
t
TCKH
Symbol
t
t
t
t
t
t
t
t
t
t
t
is the period corresponding to a frequency of 10 MHz, i.e.
TCKcyc
TCKH
TCKL
TCKr
TCKf
ASEBRKS
ASEBRKH
TDIS
TDIH
TDO
PINBRK
V
IH
t
TCKcyc
a
= −40 to 85°C, C
V
IL
Min.
50
15
15
10
1
15
15
0
2
t
t
TCKf
TCKL
V
IL
Rev.1.00 Jan. 10, 2008 Page 1605 of 1658
Max.
10
10
12
1/2V
L
V
t
= 30 pF, PLL2 on
TCKr
IH
DDQ
Unit
ns
ns
ns
ns
ns
t
ms
ns
ns
ns
t
cyc
Pcyc
32. Electrical Characteristics
Figure Remarks
32.44,
32.46
32.44
32.45
32.46
32.47
REJ09B0261-0100

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