r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1120

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

21. Serial Communication Interface with FIFO (SCIF)
(5)
Figure 21.19 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
When switching the operating mode from asynchronous mode to clocked synchronous mode
without initializing the SCIF, make sure that the ORER, PER7 to PER0, and FER7 to FER0 flags
are cleared to 0.
Rev.1.00 Jan. 10, 2008 Page 1090 of 1658
REJ09B0261-0100
No
No
Serial Data Reception (Clocked Synchronous Mode)
Read receive data in SCFRDR, and
clear RDF flag in SCFSR to 0
Read ORER flag in SCLSR
Clear RE bit in SCSCR to 0
Read RDF flag in SCFSR
All data received?
Start of reception
End of reception
ORER = 1 ?
Initialization
RDF = 1 ?
Figure 21.19 Sample Serial Reception Flowchart (1)
No
Yes
Yes
Error handling
Yes
[1]
[2]
[3]
[4]
[1]
[2]
[3]
[4]
SCIF initialization:
21.16.
Receive error handling:
perform the appropriate error handling, then clear the
ORER flag to 0.
ORER flag is set to 1.
SCIF status check and receive data read:
Read SCFSR and check that RDF = 1, then read the
receive data in SCFRDR, and clear the RDF flag to
0. The transition of the RDF flag from 0 to 1 can also
be identified by an RXI interrupt.
Serial reception continuation procedure:
trigger setting count of receive data bytes from
SCFRDR, read 1 from the RDF flag, then clear the
RDF flag to 0. The number of receive data bytes in
SCFRDR can be ascertained by reading SCRFDR.
Read the ORER flag in SCLSR to identify any error,
To continue serial reception, read at east the receive
See Sample SCIF Initialization Flowchart in figure
Transmission/reception cannot be resumed while the