r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 446

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

11. Local Bus State Controller (LBSC)
11.5.5
PCMCIA Interface
By setting the TYPE bits in CS5BCR and CS6BCR, the bus interface for the external space areas
5 and 6 can be set to the IC memory card interface or I/O card interface, which is stipulated in
JEIDA specification version 4.2 (PCMCIA 2.1).
Figure 11.15 shows the connection example of this LSI and PCMCIA card. PCMCIA card is
required to connect a three state buffer between this LSI bus interface and PCMCIA card to
perform hot swapping (a card is pulled out or plugged while the power supply of the system is
turned on).
Since operation in big endian mode is not explicitly stipulated in the JEIDA/PCMCIA standard,
this LSI only supports the little-endian PCMCIA interface with the little endian mode setting.
The PCMCIA interface space property can be selected from 8-bit common memory, 16-bit
common memory, 8-bit attribute memory, 16-bit attribute memory, 8-bit I/O space, 16-bit I/O
space, dynamic I/O bus sizing, and ATA complement mode by depending on the setting of the
SAA and SAB bits in CSnPCR.
When the first half area is accessed, the IW bit in CSnWCR and the PCWA, TEDA, and TEHA
bits in CSnPCR are selected. When the second half area is accessed, the IW bit in CSnWCR and
the PCWB, TEDB, and TEHB bits in CSnPCR are selected.
The PCWA/B1 and PCWA/B bits can be used to set the number of wait cycles to be inserted in a
low-speed bus cycle as 0, 15, 30, or 50. This value is added to the number of inserted wait cycles
specified by the IW bit in CSnWCR or PCIW bit in CSnPCR. The setup time of the address of the
RD and WE1 signals, CSn, CE2A, CE2B and REG can be set with the TEDA/B bit (with a setting
range from 0 to 15). The hold time of the address of the RD and WE1 signals, CSn, CE2A, CE2B
and REG can be set with the TEDA/B bit (with a setting range from 0 to 15).
The IW bits (IWW, IWWRD, IWWRS, IWRRD and IWRRS) in CS5BCR or CS6BCR are used to
set the number of idle cycles between cycles. The selected number of wait cycles between cycles
depends only on the area to be accessed (area 5 or 6). When area 5 is accessed, the IW bits in
CS5WCR are selected, and when area 6 is accessed, the IW bits in CS6WCR are selected.
In 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed in wraparound method according to the set bus width. The bus is not
released during this transfer.
ATA complement mode is to access the ATA device register connected to this LSI. The Device
Control Register, Alternate Status Register, Data Register, and Data Port can be accessed in ATA
Rev.1.00 Jan. 10, 2008 Page 416 of 1658
REJ09B0261-0100