r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1351

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r8a77850anbg

Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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There are several more configuration bits in non-compressed mode which will now be
demonstrated. These bits are NOT mutually exclusive, however some configurations will probably
not be useful for any other device.
They are demonstrated by referring to the following basic sample format shown in figure 26.9.
In figure 26.9, system word length of 6 bits and a data word length of 4 bits are used. Neither of
these are possible with the SSI module but are used only for clarification of the other
configuration bits.
Configuration Fields—Signal Format Fields
SSI_SCK
SSI_WS
SSI_SDATA
SWL = 6 bits (not attainable in SSI module, demonstration only)
DWL = 4 bits (not attainable in SSI module, demonstration only)
CHNL = 00, SCKP = 0, SWSP = 0, SPDP = 0, SDTA = 0, PDATA = 0, DEL = 0, MUEN = 0
4-bit data samples continuously written to SSITDR are transmitted onto the serial audio bus.
Key for this and following diagrams:
TDn
(Transmit Mode with Example System/Data Word Length)
TD28
0
1
Arrow head indicates sampling point of receiver
Bit n in SSITDR
means a low level on the serial bus (padding or mute)
means a high level on the serial bus (padding)
0
0
Figure 26.9 Basic Sample Format
TD31 TD30 TD29 TD28
1st channel
0
0
Rev.1.00 Jan. 10, 2008 Page 1321 of 1658
TD31 TD30 TD29 TD28
26. Serial Sound Interface (SSI) Module
2nd channel
0
REJ09B0261-0100
0
TD31

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