r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1222

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

24. Multimedia Card Interface (MMCIF)
(3)
Rev.1.00 Jan. 10, 2008 Page 1192 of 1658
REJ09B0261-0100
Bit
7 to 2
1
0
INTSTR2
Bit Name
⎯
FRDY_TU
FRDYI
Initial value:
Initial
Value
All 0
Undefined
0
R/W:
Bit:
—
R
R/W
R
R
R/W
7
0
—
6
0
R
Description
Reserved
These bits are always read as 0. The write
value should always be 0.
FIFO Ready Flag
Regardless of set values of DMAEN and
FRDYIE, this bit is read as 0 when FIFO
data amount matches the asserting
condition set in DMACR[2:0], and
otherwise, read as 1.
FIFO Ready Interrupt Flag
0: No interrupt
[Clearing condition]
Write 0 after reading FRDYI = 1.
(Writing 1 is invalid)
1: Interrupt requested
[Setting condition]
When remained FIFO data does not match
the assert condition set in DMACR while
DMAEN = 1 and FRDYIE = 1.
Note: FRDYI will be set on the setting
—
R
5
0
condition after clearing. To clear it,
disable the flag setting by FRDYIE in
INTCR2.
—
4
0
R
—
R
0
3
—
2
R
0
FRDY
_TU
—
R
1
FRDYI
R/W
0
0
Interrupt
output
⎯
⎯
FRDY