r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 152

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

5. Exception Handling
8. Initial page write exception in second data transfer
(2)
As a delayed branch instruction and its associated delay slot instruction are indivisible, they are
treated as a single instruction. Consequently, the priority order for exceptions that occur in these
instructions differs from the usual priority order. The priority order shown below is for the case
where the delay slot instruction has only one data transfer.
1. A check is performed for the interrupt type and re-execution type exceptions of priority levels
2. A check is performed for the interrupt type and re-execution type exceptions of priority levels
3. A check is performed for the completion type exception of priority level 2 in the delayed
4. A check is performed for the completion type exception of priority level 2 in the delay slot
5. A check is performed for priority level 3 in the delayed branch instruction and priority level 3
6. A check is performed for priority level 4 in the delayed branch instruction and priority level 4
If the delay slot instruction has a second data transfer, two checks are performed in step 2, as in
the above case (Instructions that make two accesses to memory).
If the accepted exception (the highest-priority exception) is a delay slot instruction re-execution
type exception, the branch instruction PR register write operation (PC → PR operation performed
in a BSR, BSRF, or JSR instruction) is not disabled. Note that in this case, the contents of PR
register are not guaranteed.
Rev.1.00 Jan. 10, 2008 Page 122 of 1658
REJ09B0261-0100
1 and 2 in the delayed branch instruction.
1 and 2 in the delay slot instruction.
branch instruction.
instruction.
in the delay slot instruction. (There is no priority ranking between these two.)
in the delay slot instruction. (There is no priority ranking between these two.)
Indivisible Delayed Branch Instruction and Delay Slot Instruction