r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1116

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

21. Serial Communication Interface with FIFO (SCIF)
(1)
A fixed 8-bit data format is used. No parity bit can be added.
(2)
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCIF_SCK pin can be selected as the SCIF's serial clock,
according to the settings of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For
details on SCIF clock source selection, see table 21.5.
When the SCIF is operated on an internal clock, the synchronization clock is output from the
SCIF_SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and
when no transfer is performed, the clock is fixed high. When an internal clock is selected in a
receive operation only, as long as the RE bit in SCSCR is set to 1, clock pulses are output until the
number of receive data bytes in the receive FIFO data register reaches the receive trigger count.
(3)
Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0,
then initialize the SCIF as described below.
When changing the operating mode or transfer format, etc., the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0,
SCTSR is initialized. Note that clearing the RE bit to 0 does not initialize the RDF, PER, FER, or
ORER flag state or change the contents of SCFRDR.
Figure 21.16 shows a sample SCIF initialization flowchart.
Rev.1.00 Jan. 10, 2008 Page 1086 of 1658
REJ09B0261-0100
Data Transfer Format
Clock
SCIF Initialization (Clocked Synchronous Mode)