DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 112

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.3
2.3.4
112
Function
Function
Address 0x0000 (PRR)
Address 0x0001 (PRR)
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Altern.
Altern.
Field
Reset
Reset
7-0
PA
W
W
R
R
Port A general purpose input/output data—Data Register
Port A pins 7 through 0 are associated with address outputs ADDR[15:8] respectively in expanded modes. In
emulation modes the address is multiplexed with IVD[15:8].
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
ADDR15
ADDR7
IVD15
Port A Data Register (PORTA)
Port B Data Register (PORTB)
IVD7
mux
PB7
mux
PA7
0
0
7
7
ADDR14
ADDR6
IVD14
IVD6
mux
PB6
mux
PA6
0
0
6
6
Table 2-4. PORTA Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-1. Port A Data Register (PORTA)
Figure 2-2. Port B Data Register (PORTB)
ADDR13
ADDR5
IVD13
IVD5
mux
PB5
mux
PA5
0
0
5
5
ADDR12
ADDR4
IVD12
IVD4
mux
PB4
mux
PA4
0
0
4
4
Description
ADDR11
ADDR3
IVD11
IVD3
PB3
PA3
mux
mux
3
0
3
0
ADDR10
ADDR2
IVD10
IVD2
mux
PB2
mux
PA2
0
0
2
2
Access: User read/write
Access: User read/write
Freescale Semiconductor
ADDR9
ADDR1
IVD9
IVD1
PA1
mux
PB1
mux
0
0
1
1
ADDR8
ADDR0
IVD8
IVD0
UDS
PA0
mux
PB0
mux
or
0
0
0
0
(1)
(1)