DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 558

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.3.2.22 Delay Counter Control Register (DLYCT)
Read: Anytime
Write: Anytime
All bits reset to zero.
558
Module Base + 0x0029
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
DLY[7:0]
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
7:0
W
R
DLY7
Delay Counter Select — When the PRNT bit of TSCR1 register is set to 0, only bits DLY0, DLY1 are used to
calculate the
When the PRNT bit of TSCR1 register is set to 1, all bits are used to set a more precise delay.
the delay settings in this case. After detection of a valid edge on an input capture pin, the delay counter counts
the pre-selected number of [(dly_cnt + 1)*4]bus clock cycles, then it will generate a pulse on its output if the level
of input signal, after the preset delay, is the opposite of the level before the transition.This will avoid reaction to
narrow input pulses.
Delay between two active edges of the input signal period should be longer than the selected counter delay.
Note: It is recommended to not write to this register while the timer is enabled, that is when TEN is set in register
DLY7
0
7
0
0
0
0
0
0
0
TSCR1.
DLY6
0
0
0
0
0
0
0
Table 14-29. Delay Counter Select Examples when PRNT = 1
delay.Table 14-28
DLY6
DLY1
0
Figure 14-45. Delay Counter Control Register (DLYCT)
6
0
0
1
1
DLY5
Table 14-28. Delay Counter Select when PRNT = 0
0
0
0
0
0
0
0
MC9S12XE-Family Reference Manual Rev. 1.23
Table 14-27. DLYCT Field Descriptions
DLY4
DLY5
DLY0
0
0
0
0
0
0
0
5
0
0
1
0
1
shows the delay settings in this case.
DLY3
0
0
0
0
0
0
0
DLY4
0
4
DLY2
0
0
0
0
1
1
1
Description
1024 bus clock cycles
256 bus clock cycles
512 bus clock cycles
DLY1
0
0
1
1
0
0
1
Disabled
DLY3
Delay
0
3
DLY0
0
1
0
1
0
1
0
DLY2
Disabled (bypassed)
2
0
12 bus clock cycles
16 bus clock cycles
20 bus clock cycles
24 bus clock cycles
28 bus clock cycles
8 bus clock cycles
Delay
Freescale Semiconductor
DLY1
0
1
Table 14-29
DLY0
0
0
shows