DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 85

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

is loaded with valid data from the D-Flash EEE partition. Completion of this phase is indicated by the
CCIF flag in the FTM FSTAT register becoming set. If the CPU accesses any EEE RAM location before
the CCIF flag is set, the CPU is stalled until the FTM reset sequence is complete and the EEE RAM data
is valid. Once the CCIF flag is set, indicating the end of this phase, the EEE RAM can be accessed without
impacting the CPU and FTM commands can be executed.
1.6.3.3
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.6.3.4
Refer to the PIM block description for reset configurations of all peripheral module ports.
1.6.3.5
The RAM arrays are not initialized out of reset.
1.6.3.6
The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge
of RESET from the Flash register FOPT. See
loaded from the Flash configuration field byte at global address $7FFF0E during the reset sequence.
If the MCU is secured the COP timeout rate is always set to the longest period (CR[2:0] = 111) after COP
reset.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Reset While Flash Command Active
I/O Pins
Memory
COP Configuration
FOPT Register
FOPT Register
MC9S12XE-Family Reference Manual Rev. 1.23
NV[2:0] in
Table 1-15. Initial COP Rate Configuration
NV[3] in
Table 1-16. Initial WCOP Configuration
000
001
010
011
100
101
110
111
1
0
Table 1-15
and
COPCTL Register
COPCTL Register
Table 1-16
CR[2:0] in
WCOP in
111
110
101
100
011
010
001
000
0
1
Chapter 1 Device Overview MC9S12XE-Family
for coding. The FOPT register is
85