DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 493

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.4.1.5
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. When the COP is being used, software is responsible for keeping the COP from
timing out. If the COP times out it is an indication that the software is no longer being executed in the
intended sequence; thus a system reset is initiated (see
Watchdog
allow selection of seven COP time-out periods.
When COP is enabled, the program must write $55 and $AA (in this order) to the ARMCOP register
during the selected time-out period. Once this is done, the COP time-out period is restarted. If the program
fails to do this and the COP times out, the part will reset. Also, if any value other than $55 or $AA is
written, the part is immediately reset.
Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to
the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period.
A premature write will immediately reset the part.
If PCE bit is set, the COP will continue to run in Pseudo Stop Mode.
11.4.1.6
The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting
RTIE=1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated
OSCCLK. At the end of the RTI time-out period the RTIF flag is set to one and a new RTI time-out period
starts immediately.
A write to the RTICTL register restarts the RTI time-out period.
If the PRE bit is set, the RTI will continue to run in Pseudo Stop Mode.
11.4.2
11.4.2.1
The S12XECRG block behaves as described within this specification in all normal modes.
11.4.2.2
If the external clock frequency is not available due to a failure or due to long crystal start-up time, the Bus
Clock and the Core Clock are derived from the PLLCLK running at self clock mode frequency f
mode of operation is called Self Clock Mode. This requires CME = 1 and SCME = 1, which is the default
after reset. If the MCU was clocked by the PLLCLK prior to entering Self Clock Mode, the PLLSEL bit
will be cleared. If the external clock signal has stabilized again, the S12XECRG will automatically select
OSCCLK to be the system clock and return to normal mode. See
Checker”
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
for more information on entering and leaving Self Clock Mode.
(COP)”). The COP runs with a gated OSCCLK. Three control bits in the COPCTL register
Operation Modes
Computer Operating Properly Watchdog (COP)
Real Time Interrupt (RTI)
Normal Mode
Self Clock Mode
MC9S12XE-Family Reference Manual Rev. 1.23
Section 11.4.1.5, “Computer Operating Properly
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
Section 11.4.1.4, “Clock Quality
SCM
; this
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