DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 269

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3
This section provides a detailed description of all registers accessible in the XINT module.
6.3.1
Table 6-3
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Memory Map and Register Definition
gives an overview over all XINT module registers.
Module Memory Map
0x0122–0x0125
Address
0x012C
0x012D
0x012A
0x012B
0x012E
0x012F
0x0120
0x0121
0x0126
0x0127
0x0128
0x0129
MC9S12XE-Family Reference Manual Rev. 1.23
Interrupt Request Configuration Address Register
Interrupt Request Configuration Data Register 0
Interrupt Request Configuration Data Register 1
Interrupt Request Configuration Data Register 2
Interrupt Request Configuration Data Register 3
Interrupt Request Configuration Data Register 4
Interrupt Request Configuration Data Register 5
Interrupt Request Configuration Data Register 6
Interrupt Request Configuration Data Register 7
XGATE Interrupt Priority Configuration Register
Table 6-3. XINT Memory Map
Interrupt Vector Base Register (IVBR)
(INT_CFDATA0)
(INT_CFDATA1)
(INT_CFDATA3)
(INT_CFDATA4)
(INT_CFDATA5)
(INT_CFDATA6)
(INT_CFDATA7)
(INT_CFADDR)
(INT_CFDATA2
(INT_XGPRIO)
RESERVED
RESERVED
Use
Chapter 6 Interrupt (S12XINTV2)
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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