DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 366

BOARD DEMO FOR MC9S12XEP100

DEMO9S12XEP100

Manufacturer Part Number
DEMO9S12XEP100
Description
BOARD DEMO FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of DEMO9S12XEP100

Contents
Board, Cables, CD
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DEMO9S12XEP100
Manufacturer:
PANASONIC
Quantity:
46 000
Part Number:
DEMO9S12XEP100
Manufacturer:
Freescale Semiconductor
Quantity:
135
Chapter 10 XGATE (S12XGATEV3)
10.3.1.6
The XGISP31 register is intended to point to the stack region that is used by XGATE channels of priority
3 to 1. Every time a thread of such priority is started, RISC core register R7 will be initialized with the
content of XGISP31.
Module Base +0x0006
Read: Anytime
Write: Only if XGATE requests are disabled (XGE = 0) and idle (XGCHID = $00))
10.3.1.7
The Vector Base Address Register
Section Figure 10-23., “XGATE Vector
Module Base +0x0006
Read: Anytime
Write: Only if XGATE requests are disabled (XGE = 0) and idle (XGCHID = $00))
366
Reset
Reset
XBISP74[15:1]
XBISP31[15:1]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
W
R
R
Field
15–1
Field
15–1
15
15
0
1
XGATE Initial Stack Pointer for Interrupt Priorities 3 to 1 (XGISP31)
XGATE Vector Base Address Register (XGVBR)
Figure 10-8. XGATE Initial Stack Pointer for Interrupt Priorities 3 to 1 (XGISP31)
Initial Stack Pointer— The XGISP74 register holds the initial value of RISC core register R7, for threads of
priority 7 to 4.
Initial Stack Pointer— The XGISP31 register holds the initial value of RISC core register R7, for threads of
priority 3 to 1.
14
14
0
1
= Unimplemented or Reserved
= Unimplemented or Reserved
13
13
0
1
Figure 10-9. XGATE Vector Base Address Register (XGVBR)
12
12
0
1
MC9S12XE-Family Reference Manual , Rev. 1.23
11
11
Table 10-7. XGISP74 Field Descriptions
0
Table 10-8. XGISP31 Field Descriptions
1
(Figure
10
10
0
1
Block).
10-9) determines the location of the XGATE vector block (see
0
1
9
9
XGISP31[15:1]
XGVBR[15:1]
0
0
8
8
Description
Description
0
0
7
7
6
0
6
0
0
0
5
5
0
0
4
4
0
0
3
3
Freescale Semiconductor
0
0
2
2
1
0
1
0
0
0
0
0
0
0

Related parts for DEMO9S12XEP100