DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 693

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 19
Pulse-Width Modulator (S12PWM8B8CV1)
19.1
The PWM definition is based on the HC12 PWM definitions. It contains the basic features from the HC11
with some of the enhancements incorporated on the HC12: center aligned output mode and four available
clock sources.The PWM module has eight channels with independent control of left and center aligned
outputs on each channel.
Each of the eight channels has a programmable period and duty cycle as well as a dedicated counter. A
flexible clock select scheme allows a total of four different clock sources to be used with the counters. Each
of the modulators can create independent continuous waveforms with software-selectable duty rates from
0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs.
19.1.1
The PWM block includes these distinctive features:
Freescale Semiconductor
Revision
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Number
V01.17
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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Eight independent PWM channels with programmable period and duty cycle
Dedicated counter for each PWM channel
Programmable PWM enable/disable for each channel
Software selection of PWM duty pulse polarity for each channel
Period and duty cycle are double buffered. Change takes effect when the end of the effective period
is reached (PWM counter reaches zero) or when the channel is disabled.
Programmable center or left aligned outputs on individual channels
Eight 8-bit channel or four 16-bit channel PWM resolution
Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
Programmable clock select logic
Emergency shutdown
Introduction
Revision Date
Features
08-01-2004
19.3.2.15/19-
19.6/19-723
Sections
Affected
MC9S12XE-Family Reference Manual , Rev. 1.23
710
Table 19-1.
- Added clarification of PWMIF operation in STOP and WAIT mode.
- Added notes on minimum pulse width of emergency shutdown signal.
Revision History
Description of Changes
693