DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 205

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3.2.6
Read: Anytime
Write: Anytime
These eight index bits are used to page 16 KByte blocks into the Flash page window located in the local
(CPU or BDM) memory map from address 0x8000 to address 0xBFFF (see
accessing up to 4 Mbytes of Flash (in the Global map) within the 64 KByte Local map. The PPAGE register
is effectively used to construct paged Flash addresses in the Local map format. The CPU has special access
to read and write this register directly during execution of CALL and RTC instructions..
Freescale Semiconductor
Address: 0x0015
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
PIX[7:0]
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
7–0
W
R
PIX7
Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM
array pages is to be accessed in the Program Page Window.
Program Page Index Register (PPAGE)
1
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
1
Bit21
PIX6
1
6
Figure 3-11. Program Page Index Register (PPAGE)
PPAGE Register [7:0]
MC9S12XE-Family Reference Manual Rev. 1.23
Figure 3-12. PPAGE Address Mapping
Table 3-13. PPAGE Field Descriptions
PIX5
5
1
Global Address [22:0]
CAUTION
PIX4
Bit14
NOTE
1
4
Description
Bit13
PIX3
Address: CPU Local Address
1
3
Chapter 3 Memory Mapping Control (S12XMMCV4)
Address [13:0]
or BDM Local Address
PIX2
2
1
Figure
3-12). This supports
Bit0
PIX1
1
1
PIX0
0
0
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